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Ficha personal - Javier Castro Ramirez
Nota: El investigador no está asociado a ningún departamento de la Universidad de Sevilla pero es o ha sido becario o contratado durante este año.
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits. En: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2014. Vol. 4. Núm. 2. Pag. 203-215. 10.1109/Jetcas.2014.2315878
Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
Automatic and systematic control of experimental data measurements on ASICs. 2013. Núm. 14. Pag. 45-45
Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
Automatic and systematic control of experimental data measurements on ASICs. En: Instrumentation ViewPoint. 2013. Núm. 14. Pag. 45-45
Brox Jimenez, Piedad, Castro Ramirez, Javier, Martínez Rodríguez, Macarena Cristina, Tena Sánchez, Erica, Jimenez Fernandez, Carlos Jesus, et. al.:
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions. En: IEEE Transactions on Circuits and Systems. Part 1: Regular Papers. 2013. Vol. 60. Núm. 12. Pag. 3182-3194. 10.1109/Tcsi.2013.2265962
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. En: Lecture Notes in Computer Science. 2009. Vol. 5953. Pag. 76-85. 10.1007/978-3-642-11802-9_12
Jiménez Naharro, Raúl, Parra Fernández, María del Pilar, Castro Ramirez, Javier, Sánchez Raya, Manuel, Acosta Jimenez, Antonio Jose:
Optimization of Master-Slave Flip-Flops for High-Performance Applications. En: Lecture Notes in Computer Science. 2006. Vol. 4148. Pag. 439-449
Parra Fernández, María del Pilar, Castro Ramirez, Javier, Valencia Barrero, Manuel, Acosta Jimenez, Antonio Jose:
Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits. En: Proceedings of SPIE: The International Society for Optical Engineering. 2005. Vol. 5837. Pag. 1003-1014. 10.1117/12.608276
Low-Power Differential Logic Gates for DPA Resistant Circuits. Poster en Congreso. Euromicro Conference on Digital System Design. Verona. 2014
Tena Sánchez, Erica, Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
Design and Test of a Low-Power 90nm Xor/Xnor Gate for Cryptographic Applications. Comunicación en congreso. International Workshop On Power And Timing Modeling, Optimization And Simulations. Palma de Mallorca. 2014
Tena Sánchez, Erica, Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
Automatic and Systematic Control of Experimental Data Measurements on ASICs. Comunicación en congreso. 19th Symposium IMEKO TC 4 Symposium. Barcelona, - BARCELONA, ESPAÑA. 2013
Tena Sánchez, Erica, Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
Automatic and Systematic Test Toolset for Digital ASICs. Comunicación en congreso. DCIS 2013. Donostia - San Sebastián (España). 2013
Eiroa Lorenzo, Susana, Castro Ramirez, Javier, Martínez Rodríguez, Macarena Cristina, Tena Sánchez, Erica, Brox Jimenez, Piedad, et. al.:
Reducing bit flipping problems in SRAM physical unclonable functions for chip identification. Comunicación en congreso. 19th International Conference on Electronics, Circuits and Systems. Seville (Spain). 2012
Martínez Rodríguez, Macarena Cristina, Brox Jimenez, Piedad, Castro Ramirez, Javier, Tena Sánchez, Erica, Acosta Jimenez, Antonio Jose, et. al.:
ASIC-in-the-loop methodology for verification of piecewise affine controllers. Comunicación en congreso. 19th International Conference on Electronics, Circuits and Systems. Seville (Spain). 2012
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
Optimization of Clock-Gating Structures for Low-Leakage High-Performance Applications. Comunicación en congreso. IEEE International Symposium on Circuits and Systems, ISCAS, pp. 1979-1982, Jun. 201. Paris, France. 2010. Proceedings of 2010 IEEE International Symposium on Circuits Ans Systems (ISCAS). 3220. 3223
Castro Ramirez, Javier, Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
An Improved Differential Pull-Down Network Logic Configuration for Dpa Resistant Circuits. Comunicación en congreso. The 22nd International Conference on Microelectronics. El Cairo, Egipto. 2010
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
Revisiting Clock-Gating: the Common Place for Power Reduction. Comunicación en congreso. XVI Workshop IBERCHIP. Iguazu Falls, Brasil. 2010. XVI Workshop IBERCHIP. -. -
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
Master-Slave Flip-Flop Optimization for Fine-Grained Clock-Gating Applications. Comunicación en congreso. IEEE Latin American Symposium on Circuits and Systems. Brasil. 2010
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. Comunicación en congreso. Nineteenth International Workshop on Power and Timing Modeling, Optimization and Simulation. Delft, Países Bajos. 2009. Lecture Notes in Computer Science, 2010, Volume 5953/2010. 76. 85
Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose, Vesterbacka, Mark:
Geometry Optimization in Basic CMOS Cells for Improved Power, Leakage, and Noise Performances. Comunicación en congreso. Int. Conf. on Advances in Electronics and Micro-Electronics. 2008. Int. Conf. on Advances in Electronics and Micro-Electronics (Enics'08). 48. 53
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Valencia Barrero, Manuel, Acosta Jimenez, Antonio Jose:
Asymmetric Clock Driver for Improved Power and Noise Performances. Comunicación en congreso. IEEE International Symposium on Circuits and Systems (ISCAS 2007). New Orleans, USA. 2007. Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on. 893. 896
Acosta Jimenez, Antonio Jose, Mora Gutierrez, Jose Miguel, Castro Ramirez, Javier, Parra Fernández, María del Pilar:
Effects of Buffer Insertion on the Average/Peak Power Ratio in CMOS VLSI Digital Circuits. Comunicación en congreso. VLSI Circuits and Systems Conference SPIE 2007. Maspalomas, España. 2007. VLSI Circuits and Systems Conference SPIE 2007. 1007. 1014
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
A Methodology for Switching Noise Estimation At a Gate Level. Comunicación en congreso. VLSI Circuits and Systems Conference SPIE 2007. Maspalomas, España. 2007. VLSI Circuits and Systems Conference SPIE 2007. 1000. 1006
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Valencia Barrero, Manuel, Acosta Jimenez, Antonio Jose:
A Switching Noise Vision of the Optimization Techniques for Low-Power Synthesis. Comunicación en congreso. European Conference on Circuit Theory and Design ECCTD . Santander (ESPAÑA). 2007. European Conference on Circuit Theory and Design ECCTD 2007. 156. 159
Sánchez Raya, Manuel, Jiménez Naharro, Raúl, Castro Ramirez, Javier:
Prototype Board for the Test of Self-Timed Circuits Developed in FPGAS. Poster en Congreso. Conference on VLSI Circuits and Systems II. Santander (ESPAÑA). 2005
Parra Fernández, María del Pilar, Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
Application of Clock Gating Techniques At a Flip-Flop Level to Switching Noise Reduction in VLSI Circuits. Comunicación en congreso. Conference on VLSI Circuits and Systems II. Santander (ESPAÑA). 2005. VLSI Circuits and Systems II. 1003. 1014
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
Performance Analysis of Full Adders in CMOS Technologies. Comunicación en congreso. Conference on VLSI Circuits and Systems II. Santander (ESPAÑA). 2005. VLSI Circuits and Systems II. 38. 48
Parra Fernández, María del Pilar, Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
A Methodology for the Characterization of Arithmetic Circuits on CMOS Deep Submicron Technologies. Comunicación en congreso. Conference on VLSI Circuits and Systems II. Santander (ESPAÑA). 2005. VLSI Circuits and Systems II. 902. 913
Brox Jimenez, Piedad, Martínez Rodríguez, Macarena Cristina, Baturone Castillo, Iluminada, Acosta Jimenez, Antonio Jose, Castro Ramirez, Javier:
Método y dispositivo para generar identificadores y números verdaderamente aleatorios. Patente de invención, Propiedad industrial. Solicitud: 2014-03-20
Acosta Jimenez, Antonio Jose, Baturone Castillo, Iluminada, Castro Ramirez, Javier, Jimenez Fernandez, Carlos Jesus, Martínez Rodríguez, Macarena Cristina:
Method for generating piecwise-affine multivariable functions with on-line computation of the search tree and device for implementing same. Patente de invención, Propiedad industrial. Solicitud: 2013-06-04
Acosta Jimenez, Antonio Jose, Baturone Castillo, Iluminada, Castro Ramirez, Javier, Jimenez Fernandez, Carlos Jesus, Brox Jimenez, Piedad, et. al.:
Método para generar funciones multivariables afines a tramos con computación on-line del árbol de búsqueda y dispositivo para implementación del método. Patente de invención, Propiedad industrial. Solicitud: 2012-06-04
Javier Castro Ramirez
Telefono: 955056666
Email: Solicitar correo
Participa en los siguientes proyectos/ayudas en la US:
- Proyecto de investigación:
- Circuitos Integrados para Transmisión de Información Especialmente Segura (TEC2010-16870 - Investigador)
- Model-based synthesis of digital electronic circuits for embedded control (MOBY-DIC) (FP7-ICT-2009-4-248858 - Contratado)
- Diseño Microelectrónico para Autenticación Cripto-Biométrica (P08-TIC-03674 - Contratado Postdoctoral)
- Diseño de sistemas digitales micro-nanoelectrónicos de altas prestaciones (EXC/2005/TIC-635 - Otro Investigador)
- Ayuda a la investigación:
- Incentivo al Grupo de Investigación TIC-180 (2011/TIC-180 - Investigador)
- Ayuda a la Consolidación del Grupo de Investigación TIC-180 (2008/TIC-180 - Investigador)
- Ayuda a la Consolidación del Grupo de Investigación TIC-180 (2007/TIC-180 - Investigador)
Cobertura de la base de datos de proyectos, véase aqui
Publicaciones:
Publicaciones en Revistas
Tena Sánchez, Erica, Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits. En: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2014. Vol. 4. Núm. 2. Pag. 203-215. 10.1109/Jetcas.2014.2315878
Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
Automatic and systematic control of experimental data measurements on ASICs. 2013. Núm. 14. Pag. 45-45
Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
Automatic and systematic control of experimental data measurements on ASICs. En: Instrumentation ViewPoint. 2013. Núm. 14. Pag. 45-45
Brox Jimenez, Piedad, Castro Ramirez, Javier, Martínez Rodríguez, Macarena Cristina, Tena Sánchez, Erica, Jimenez Fernandez, Carlos Jesus, et. al.:
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions. En: IEEE Transactions on Circuits and Systems. Part 1: Regular Papers. 2013. Vol. 60. Núm. 12. Pag. 3182-3194. 10.1109/Tcsi.2013.2265962
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. En: Lecture Notes in Computer Science. 2009. Vol. 5953. Pag. 76-85. 10.1007/978-3-642-11802-9_12
Jiménez Naharro, Raúl, Parra Fernández, María del Pilar, Castro Ramirez, Javier, Sánchez Raya, Manuel, Acosta Jimenez, Antonio Jose:
Optimization of Master-Slave Flip-Flops for High-Performance Applications. En: Lecture Notes in Computer Science. 2006. Vol. 4148. Pag. 439-449
Parra Fernández, María del Pilar, Castro Ramirez, Javier, Valencia Barrero, Manuel, Acosta Jimenez, Antonio Jose:
Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits. En: Proceedings of SPIE: The International Society for Optical Engineering. 2005. Vol. 5837. Pag. 1003-1014. 10.1117/12.608276
Aportaciones a Congresos
Tena Sánchez, Erica, Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:Low-Power Differential Logic Gates for DPA Resistant Circuits. Poster en Congreso. Euromicro Conference on Digital System Design. Verona. 2014
Tena Sánchez, Erica, Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
Design and Test of a Low-Power 90nm Xor/Xnor Gate for Cryptographic Applications. Comunicación en congreso. International Workshop On Power And Timing Modeling, Optimization And Simulations. Palma de Mallorca. 2014
Tena Sánchez, Erica, Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
Automatic and Systematic Control of Experimental Data Measurements on ASICs. Comunicación en congreso. 19th Symposium IMEKO TC 4 Symposium. Barcelona, - BARCELONA, ESPAÑA. 2013
Tena Sánchez, Erica, Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
Automatic and Systematic Test Toolset for Digital ASICs. Comunicación en congreso. DCIS 2013. Donostia - San Sebastián (España). 2013
Eiroa Lorenzo, Susana, Castro Ramirez, Javier, Martínez Rodríguez, Macarena Cristina, Tena Sánchez, Erica, Brox Jimenez, Piedad, et. al.:
Reducing bit flipping problems in SRAM physical unclonable functions for chip identification. Comunicación en congreso. 19th International Conference on Electronics, Circuits and Systems. Seville (Spain). 2012
Martínez Rodríguez, Macarena Cristina, Brox Jimenez, Piedad, Castro Ramirez, Javier, Tena Sánchez, Erica, Acosta Jimenez, Antonio Jose, et. al.:
ASIC-in-the-loop methodology for verification of piecewise affine controllers. Comunicación en congreso. 19th International Conference on Electronics, Circuits and Systems. Seville (Spain). 2012
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
Optimization of Clock-Gating Structures for Low-Leakage High-Performance Applications. Comunicación en congreso. IEEE International Symposium on Circuits and Systems, ISCAS, pp. 1979-1982, Jun. 201. Paris, France. 2010. Proceedings of 2010 IEEE International Symposium on Circuits Ans Systems (ISCAS). 3220. 3223
Castro Ramirez, Javier, Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
An Improved Differential Pull-Down Network Logic Configuration for Dpa Resistant Circuits. Comunicación en congreso. The 22nd International Conference on Microelectronics. El Cairo, Egipto. 2010
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
Revisiting Clock-Gating: the Common Place for Power Reduction. Comunicación en congreso. XVI Workshop IBERCHIP. Iguazu Falls, Brasil. 2010. XVI Workshop IBERCHIP. -. -
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
Master-Slave Flip-Flop Optimization for Fine-Grained Clock-Gating Applications. Comunicación en congreso. IEEE Latin American Symposium on Circuits and Systems. Brasil. 2010
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. Comunicación en congreso. Nineteenth International Workshop on Power and Timing Modeling, Optimization and Simulation. Delft, Países Bajos. 2009. Lecture Notes in Computer Science, 2010, Volume 5953/2010. 76. 85
Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose, Vesterbacka, Mark:
Geometry Optimization in Basic CMOS Cells for Improved Power, Leakage, and Noise Performances. Comunicación en congreso. Int. Conf. on Advances in Electronics and Micro-Electronics. 2008. Int. Conf. on Advances in Electronics and Micro-Electronics (Enics'08). 48. 53
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Valencia Barrero, Manuel, Acosta Jimenez, Antonio Jose:
Asymmetric Clock Driver for Improved Power and Noise Performances. Comunicación en congreso. IEEE International Symposium on Circuits and Systems (ISCAS 2007). New Orleans, USA. 2007. Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on. 893. 896
Acosta Jimenez, Antonio Jose, Mora Gutierrez, Jose Miguel, Castro Ramirez, Javier, Parra Fernández, María del Pilar:
Effects of Buffer Insertion on the Average/Peak Power Ratio in CMOS VLSI Digital Circuits. Comunicación en congreso. VLSI Circuits and Systems Conference SPIE 2007. Maspalomas, España. 2007. VLSI Circuits and Systems Conference SPIE 2007. 1007. 1014
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
A Methodology for Switching Noise Estimation At a Gate Level. Comunicación en congreso. VLSI Circuits and Systems Conference SPIE 2007. Maspalomas, España. 2007. VLSI Circuits and Systems Conference SPIE 2007. 1000. 1006
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Valencia Barrero, Manuel, Acosta Jimenez, Antonio Jose:
A Switching Noise Vision of the Optimization Techniques for Low-Power Synthesis. Comunicación en congreso. European Conference on Circuit Theory and Design ECCTD . Santander (ESPAÑA). 2007. European Conference on Circuit Theory and Design ECCTD 2007. 156. 159
Sánchez Raya, Manuel, Jiménez Naharro, Raúl, Castro Ramirez, Javier:
Prototype Board for the Test of Self-Timed Circuits Developed in FPGAS. Poster en Congreso. Conference on VLSI Circuits and Systems II. Santander (ESPAÑA). 2005
Parra Fernández, María del Pilar, Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
Application of Clock Gating Techniques At a Flip-Flop Level to Switching Noise Reduction in VLSI Circuits. Comunicación en congreso. Conference on VLSI Circuits and Systems II. Santander (ESPAÑA). 2005. VLSI Circuits and Systems II. 1003. 1014
Castro Ramirez, Javier, Parra Fernández, María del Pilar, Acosta Jimenez, Antonio Jose:
Performance Analysis of Full Adders in CMOS Technologies. Comunicación en congreso. Conference on VLSI Circuits and Systems II. Santander (ESPAÑA). 2005. VLSI Circuits and Systems II. 38. 48
Parra Fernández, María del Pilar, Castro Ramirez, Javier, Acosta Jimenez, Antonio Jose:
A Methodology for the Characterization of Arithmetic Circuits on CMOS Deep Submicron Technologies. Comunicación en congreso. Conference on VLSI Circuits and Systems II. Santander (ESPAÑA). 2005. VLSI Circuits and Systems II. 902. 913
Patentes:
Brox Jimenez, Piedad, Martínez Rodríguez, Macarena Cristina, Baturone Castillo, Iluminada, Acosta Jimenez, Antonio Jose, Castro Ramirez, Javier:
Método y dispositivo para generar identificadores y números verdaderamente aleatorios. Patente de invención, Propiedad industrial. Solicitud: 2014-03-20
Acosta Jimenez, Antonio Jose, Baturone Castillo, Iluminada, Castro Ramirez, Javier, Jimenez Fernandez, Carlos Jesus, Martínez Rodríguez, Macarena Cristina:
Method for generating piecwise-affine multivariable functions with on-line computation of the search tree and device for implementing same. Patente de invención, Propiedad industrial. Solicitud: 2013-06-04
Acosta Jimenez, Antonio Jose, Baturone Castillo, Iluminada, Castro Ramirez, Javier, Jimenez Fernandez, Carlos Jesus, Brox Jimenez, Piedad, et. al.:
Método para generar funciones multivariables afines a tramos con computación on-line del árbol de búsqueda y dispositivo para implementación del método. Patente de invención, Propiedad industrial. Solicitud: 2012-06-04
Vicerrectorado de Investigación. Universidad de Sevilla.
Pabellón de Brasil. Paseo de las Delicias s/n. Sevilla