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Ficha personal - Juan Nuñez Martínez


Nota: El investigador no está asociado a ningún departamento de la Universidad de Sevilla pero es o ha sido becario o contratado durante este año.

Juan Nuñez Martínez
Telefono: 954466666
Email: Solicitar correo
Perfil en ORCID: 0000-0002-0279-9472
Perfil en Scopus: 57203635378

Grupo de Investigación: Diseño y Test de Circuitos Integrados de Señal Mixta

Participa en los siguientes proyectos/ayudas en la US:

  • Proyecto de investigación:
    • Two-Dimensional Oscillatory Neural Networks for Energy Efficent Neuromorphic computing (NeurONN) (H2020-871501 - Contratado)
    • Circuitos y Arquitecturas con Dispositivos Steep Slope para Aplicaciones de muy Bajo Consumo de Potencia (TEC2017-87052-P - Equipo Trabajo (Solicitud))
    • Dispositivos, Circuitos y Arquitecturas Fiables y de Bajo Consumo para Iot (TEC2016-75151-C3-3-R - Contratado)
    • Nano-Arquitecturas para Computación Lógica Usando Dispositivos Emergentes (TEC2013-40670-P - Equipo Trabajo (Solicitud))
    • Aproximación Multinivel al Diseño Orientado a la Fiabilidad de Circuitos Integrados Analógicos y Digitales (TEC2013-45638-C3-3-R - Contratado)
    • Flexics: Técnicas de Diseño de Circuitos y Sistemas Micro-Nanoelectrónicos Flexibles y Reconfigurables de Bajo Consumo y Bajo Coste Aplicados a Comunicaciones Inalámbricas (P12-TIC-1481 - Contratado)
    • Adaptando el Diseño y Test de Circuitos Integrados de Señal Mixta y de Rf a las Variaciones del Proceso y del Entorno (TEC2011-28302 - Contratado)
    • Arquitecturas y Circuitos con Rtds para Aplicaciones Lógicas y no Lineales (TEC2010-18937 - Investigador)
    • Diseño e implementación de circuitos multivaluados usando dispositivos con característica Ndr (P07-TIC-02961 - Otro Investigador)
    • Técnicas de diseño y test de circuitos integrados mixtos en tecnologías emergentes (EXC/2005/TIC-927 - Otro Investigador)

  • Ayuda a la investigación:
    • Incentivo al Grupo de Investigación TIC-178 (2017/TIC-178 - Investigador)
    • Incentivo al Grupo de Investigación TIC-178 (2011/TIC-178 - Investigador)
    • Ayuda a la Consolidación del Grupo de Investigación TIC-178 (2009/TIC-178 - Investigador)
    • Ayuda a la Consolidación del Grupo de Investigación TIC-178 (2008/TIC-178 - Investigador)
    • Ayuda a la Consolidación del Grupo de Investigación TIC-178 (2007/TIC-178 - Investigador)

Cobertura de la base de datos de proyectos, véase aqui


Publicaciones:

Capítulos en Libros
Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Analytic Approach to the Operation of Rtd Ternary Inverters Based on Mml. Pag. 97-112. En: Cutting Edge Nanotechnology. Rijeka, Croacia. In-Tech. 2010. ISBN 978-953-7619-93-0

Publicaciones en Revistas
Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Jiménez, Manuel, Todri Sanial, Aida, et. al.:
Insights into the Dynamics of VO2 Coupled Oscillators for ONNs. En: IEEE Transactions on Circuits and Systems. Part 2: Express Briefs. 2021. https://doi.org/10.1109/TCSII.2021.3085133

Todri Sanial, Aida, Carapezzi, Stefania, Delacour, Corentin, Abernot, Madeleine, Gil, Thierry, et. al.:
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase. En: IEEE Transactions on Neural Networks and Learning Systems. 2021

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Jiménez, Manuel, Quintana Toledo, Jose Maria, Todri Sanial, Aida, et. al.:
Oscillatory Neural Networks Using VO2 Based Phase Encoded Logic. En: Frontiers in Neuroscience. 2021. https://doi.org/10.3389/fnins.2021.655823

Abernot, Madeleine, Gil, Thierry, Jiménez, Manuel, Nuñez Martínez, Juan, Avedillo de, Maria Jose, et. al.:
Digital Implementation of Oscillatory Neural Network for Image Recognition Applications. En: Frontiers in Neuroscience. 2021. https://doi.org/10.3389/fnins.2021.713054

Delgado Lozano, Ignacio M., Tena Sánchez, Erica, Nuñez Martínez, Juan, Acosta Jimenez, Antonio Jose:
Design and analysis of secure emerging crypto-hardware using HyperFET devices. En: IEEE Transactions on Emerging Topics in Computing. 2020. Vol. Online. 10.1109/Tetc.2020.2977735

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Approaching the Design of Energy Recovery Logic Circuits using Tunnel Transistors. En: IEEE Transactions on Nanotechnology. 2020. Vol. 19. Pag. 500-507. 10.1109/Tnano.2020.3004941

Delgado Lozano, I. M., Tena Sánchez, Erica, Nuñez Martínez, Juan, Acosta Jimenez, Antonio Jose:
Projection of dual-rail DPA countermeasures in future FinFET and emerging TFET technologies. En: ACM Journal on Emerging Technologies in Computing Systems. 2020. Vol. 16. Núm. 3. Pag. 1-16. 10.1145/3381857

Jiménez, Manuel, Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Hybrid Phase Transition FET Devices for Logic Computation. En: IEEE Journal on Exploratory Solid-State Computatio. 2020. Vol. 6. Núm. 1. Pag. 1-8. 10.1109/Jxcdc.2020.2993313

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Nuñez Martínez, Juan:
Phase Transition Device for Phase Storing. En: IEEE Transactions on Nanotechnology. 2020. Pag. 107-112. 10.1109/Tnano.2020.2965243

Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Phase Transition Device for Phase Storing. 2020. Pag. 107-112. 10.1109/Tnano.2020.2965243

Avedillo de, Maria Jose, Jiménez, Manuel, Nuñez Martínez, Juan:
Phase Transition FETs for Improved Dynamic Logic Gates. En: IEEE Electron Device Letters. 2018. Vol. 39. Núm. 11. Pag. 1776-1779. 10.1109/Led.2018.2871855

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Power and Speed Evaluation of Hyper-FET Circuits. En: IEEE Access. 2018. Vol. 7. Pag. 6724-6732. 10.1109/Access.2018.2889016

Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Impact of the RT¿level architecture on the power performance of tunnel transistor circuits. En: International Journal of Circuit Theory and Applications. 2017. Vol. 46. Núm. 3. Pag. 647-655. https://doi.org/10.1002/cta.2398

Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Insights Into the Operation of Hyper-FET-Based Circuits. En: IEEE Transactions on Electron Devices. 2017. Vol. 64. Núm. 9. Pag. 3912-3918. 10.1109/Ted.2017.2726765

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Reducing the impact of reverse currents in tunnel FET rectifiers for energy harvesting applications. En: IEEE Journal of the Electron Devices Society. 2017. Vol. 5. Núm. 6. Pag. 530-534. 10.1109/Jeds.2017.2737598

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Comparative Analysis of Projected Tunnel and CMOS Transistors for Distinct Logic Applications Areas. En: IEEE Transactions on Electron Devices. 2016. Vol. 63. Núm. 12. Pag. 5012-5020. 10.1109/Ted.2016.2616891

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs. En: IEEE Transactions on Nanotechnology. 2016. Vol. 16. Núm. 1. Pag. 83-89. 10.1109/Tnano.2016.2629264

Nuñez Martínez, Juan, Gines Arteaga, Antonio Jose, Peralias Macias, Eduardo, Rueda Rueda, Adoracion:
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs. En: Analog Integrated Circuits and Signal Processing. 2016. Vol. 89. Núm. 3. Pag. 593-609. 10.1007/s10470-016-0870-6

Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Improving speed of Tunnel FETs logic circuits. En: Electronics Letters. 2015. Vol. 51. Núm. 21. Pag. 1702-1704. 10.1049/el.2015.2416

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monoestable to Bistable Logic Elements. En: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014. Vol. 22. Núm. 10. Pag. 2238-2242. 10.1109/Tvlsi.2013.2283306

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Novel Pipeline Architectures based on Negative Differential Resistance Devices. En: Microelectronics Journal. 2013. Vol. 44. Núm. 9. Pag. 807-813. 10.1016/j.mejo.2013.06.012

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Two-Phase RTD-CMOS Pipelined Circuits. En: IEEE Transactions on Nanotechnology. 2012. Vol. 11. Núm. 6. Pag. 1063-1069. 10.1109/Tnano.2012.2213839

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Domino inspired MOBILE networks. En: Electronics Letters. 2012. Vol. 48. Núm. 5. Pag. 292-293

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
RTD-CMOS Pipelined Networks for Reduced Power Consumption. En: IEEE Transactions on Nanotechnology. 2011. Vol. 10. Núm. 6. Pag. 1217-1220

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Simplified single-phase clock scheme for MOBILE networks. En: Electronics Letters. 2011. Vol. 47. Núm. 11. Pag. 648-650

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Pettenghi Roldan, Hector, Nuñez Martínez, Juan:
Operation Limits for Rtd-Based Mobile Circuits. En: IEEE Transactions on Circuits and Systems Part I: Fundamental Theory and Applications. 2009. Vol. 56. Núm. 2. Pag. 350-363

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Efficient Realisation of MOS-Ndr Threshold Logic Gates. En: Electronics Letters. 2009. Vol. 45. Núm. 23. Pag. 1158-1160

Aportaciones a Congresos
Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Steep-slope Devices for Power Efficient Adiabatic Logic Circuits. Comunicación en congreso. XXXV Conference on Design of Circuits and Integrated Systems. Segovia. 2020

Jiménez, Manuel, Nuñez Martínez, Juan, Avedillo de, Maria Jose:
An Approach to the Device-Circuit Co-Design of HyperFET Circuits. Comunicación en congreso. International Symposium on Circuits and Systems. Sevilla, España. 2020

Martín, Pablo, Nuñez Martínez, Juan, Roca, E., Castro López, Rafael, Martin Martinez, Javier, et. al.:
An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks. Comunicación en congreso. 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). Lausanne, ALPINE CENTER PIORA, SWITZERLAND. 2019

Nuñez Martínez, Juan, Roca, E., Castro López, Rafael, Martin Martinez, Javier, Rodriguez, Rosana, et. al.:
Experimental Characterization of Time-Dependent Variability in Ring Oscillators. Comunicación en congreso. 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). Lausanne, ALPINE CENTER PIORA, SWITZERLAND. 2019

Nuñez Martínez, Juan, Jiménez, Manuel, Avedillo de, Maria Jose:
Device circuit co-design of HyperFET transistors. Comunicación en congreso. 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS). Bilbao (España). 2019

Tena Sánchez, Erica, Delgado Lozano, Ignacio M., Nuñez Martínez, Juan, Acosta Jimenez, Antonio Jose:
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. Comunicación en congreso. XXXIII Conference on Design of Circuits and Integrated Systems. - Lyon, Francia, Francia. 2018

Nuñez Martínez, Juan:
Impact of TFET Reverse Currents Into Circuit Operation: A Case Study. Comunicación en congreso. 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Granada. 2018

Quintero Alvarez, Héctor Javier, Jiménez, Manuel, Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Inverting versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. Comunicación en congreso. 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. - Praga, República Checa. 2018

Saraza Canflanca, Pablo, Malagon, Daniel, Moreira, Fabio, Toro Frías, Antonio, Nuñez Martínez, Juan, et. al.:
Design considerations of an SRAM array for the statistical validation of time-dependent variability models. Comunicación en congreso. 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. - Praga, República Checa. 2018

Fiorelli Martegani, Rafaella Bianca, Nuñez Martínez, Juan, Silveira, Fernando:
All-Inversion Region gm/Id Methodology for RF Circuits in FinFET Technologies. Comunicación en congreso. 16th IEEE International NEWCAS Conference. - Montreal, Canadá. 2018

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Exploring Logic Architectures Suitable for TFETs Devices. Comunicación en congreso. 2017 IEEE International Symposium on Circuits and Systems (ISCAS). Baltimore, MD, USA. 2017

Tena Sánchez, Erica, Acosta Jimenez, Antonio Jose, Nuñez Martínez, Juan:
Secure Cryptographic Hardware Implementation Issues for High-Performance Applications. Poster en Congreso. 26th International Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS). Bremen, Alemania. 2016

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Complementary Tunnel Gate Topology to Reduce Crosstalk Effects. Comunicación en congreso. XXXI Conference on Design of Circuits and Integrated Systems DCIS 2016. Granada. 2016

Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Impact of Pipeline in the Power Performance of Tunnel Transistor Circuits. Comunicación en congreso. 26th International Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS). Bremen, Alemania. 2016

Nuñez Martínez, Juan, Gines Arteaga, Antonio Jose, Peralias Macias, Eduardo, Rueda Rueda, Adoracion:
Low-jitter differential clock driver circuits for high-performance high-resolution ADCs. Comunicación en congreso. Design of Integrated Circuits and Systems. Estoril (Portugal). 2015

Nuñez Martínez, Juan, Gines Arteaga, Antonio Jose, Peralias Macias, Eduardo, Rueda Rueda, Adoracion:
An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs. Comunicación en congreso. IEEE 6th Latin American Symposium on Circuits & Systems. Buenos Aires (Argentina)-Montevideo (Uruguay). 2015

Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Assessing application areas for tunnel transistor technologies. Comunicación en congreso. Design of Integrated Circuits and Systems 2015. Lisboa. 2015

Quintero Alvarez, Héctor Javier, Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Improving robustness of dynamic logic based pipelines. Comunicación en congreso. Design of Circuits and Integrated Systems 2015. 2015

Nuñez Martínez, Juan, Quintero Alvarez, Héctor Javier, Avedillo de, Maria Jose:
DOE based high-performance gate-level pipelines. Comunicación en congreso. Powe and Timming Modeling, Optimization and Simulation International Workshop. Palma de Mallorca. 2014

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Quintero Alvarez, Héctor Javier:
Improving delay-noise trade-off of dynamic gates for fine-grained pipelined applications. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems. 2013

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Novel dynamic gate topology for superpipelines in DSM technologies. Comunicación en congreso. Digital System Design EUROMICRO. Santander. 2013

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits. Comunicación en congreso. IEEE International Conference on Electronics, Circuits, and Systems. Sevilla, España. 2012

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications. Comunicación en congreso. International Workshop on Power and Timing Modeling, Optimization and Simulation. NEWCASTLE, REINO UNIDO, United Kingdom. 2012

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits. Comunicación en congreso. IBERCHIP 2012. Playa del Carmen, Mexico. 2012

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Compact and Power Efficient MOS-NDR Muller C-Elements. Comunicación en congreso. Doctoral Conference on Computing, Electrical and Industrial Systems. Caparica (Lisboa). 2012

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs. Comunicación en congreso. SPIE 2011. Praga, República Checa. 2011

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Efficient Realization of RTD-CMOS Logic Gates. Comunicación en congreso. Great Lakes Symposium on VLSI. Laussane, Suiza. 2011

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Evaluation of Rtd-CMOS Logic Gates. Comunicación en congreso. DSD Euromicro 2010. Lille, Francia. 2010. DSD Euromicro 2010. 621. 627

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Single Phase MOS-Ndr Mobile Networks. Comunicación en congreso. IEEE International Symposium on Circuits and Systems, ISCAS, pp. 1979-1982, Jun. 201. Paris, France. 2010. Proceedings of 2010 IEEE International Symposium on Circuits Ans Systems (ISCAS). 153. 156

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Redes Mobile MOS-Ndr Operando con Reloj de una Fase. Comunicación en congreso. IBERCHIP 2010. Iguazú (Brasil). 2010. IBERCHIP 2010. 145. 148

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Pettenghi Roldan, Hector, Nuñez Martínez, Juan:
Puertas Umbral Generalizadas para el Diseño Lógicos de Circuitos Mobile. Comunicación en congreso. IBERCHIP. Buenos Aires, Argentina. 2009. IBERCHIP 2009. -. -

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Muller C-Elements Multientrada Basados en MOS-Ndr. Comunicación en congreso. IBERCHIP. Buenos Aires, Argentina. 2009. IBERCHIP 2009. -. -

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Fast and Area Efficient Multi-Input Muller C-Element Based on MOS-Ndr. Comunicación en congreso. IEEE International Symposium on Circuits and Systems. Taipei, Taiwan. 2009. IEEE International Symposium on Circuits and Systems. 1811. 1814

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
DC Operation Limits for Mobile Inverters. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems. Zaragoza. 2009. XXI Conference on Design of Circuits and Integrated Systems. --. --

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
A Quasi Differential Quantizer Based on Smobile. Comunicación en congreso. IEEE Symposium on Integrated Circuits and Systems Design . Río de Janeiro (Brazil). 2008. IEEE Proceedings of the 20th Symposium on Integrated Circuits and Systems Design (Sbcci'2007). 251. 256

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Limits to a Correct Operation in Rtd-Based Ternary Inverters. Comunicación en congreso. ISCAS 2008. Seattle, Washington, USA. 2008. IEEE International Symposium on Circuits and Systems. 604. 607

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Design of Rtd-Based Nmin/Nmax Gates. Comunicación en congreso. IEEE Nano 2008. Arlingtong, Tx, USA. 2008. 8th IEEE Conference on Nanotechnology, 2008. . 518. 521

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Holding Preserving in Rtd-Based Multiple-Valued Quantiziers. Comunicación en congreso. IEEE Conference on Nanotechnology . Hong-Kong (China). 2007. IEEE Conference on Nanotechnology (IEEE Nano'2007). --. --

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Analytic Approach to the Operation of Rtd Ternary Inverters Based on Mml. Comunicación en congreso. International Workshop on Post-Binary Ulsi Systems. Oslo (Norway). 2007. International Workshop on Post-Binary Ulsi Systems. --. --

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Limits to a Correct Evaluation in Rtd-Based Quaternary Inverters. Comunicación en congreso. International Symposium on Multiple-Valued Logic. Oslo (Norway). 2007. International Symposium on Multiple-Valued Logic (Ismvl'2007). 51. 56

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Operation Limits in Rtd-Based Ternary Quantizers. Comunicación en congreso. ACM Great Lakes Symposium on VLSI. Stressa-Lago Maggiore (Italy). 2007. ACM Great Lakes Symposium on VLSI (Glsvlsi'2007). 114. 119

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Correct DC Operation in Rtd Based Ternary Inverters. Comunicación en congreso. IEEE International Conference of Nano/Micro Engineered and Molecular Systems. Bangkok (Thailandia). 2007. IEEE International Conference of Nano/Micro Engineered and Molecular Systems (Nems'2007). 860. 865

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
DC Operation Limits of Rtd Ternary Inverters Based on Nml. Comunicación en congreso. DCIS. Santander (ESPAÑA). 2007. DCIS 2007. 311. 316

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Correct Operation in Smobile-Based Quasi-Differential Quantiziers. Comunicación en congreso. ECCTD 2007. Santander (ESPAÑA). 2007. ECCTD 2007: European Conference on Cicuit Theory and Design. 930. 933

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Nuñez Martínez, Juan:
DC Correct Operation in Mobile Inverters. Comunicación en congreso. Mwcas 2006. San Juan (Puerto Rico). 2006. 49th Midwest Symposium on Circuits and Systems. --. --

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Limits to a Correct Evaluation in Rtd Based Ternary Inverters. Comunicación en congreso. Icecs. Nice (France). 2006. IEEE International Conference on Electronics , Circuits, and Systems. 403. 406

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Holding Dissapearance in Rtd-Based Quantizers. Comunicación en congreso. Ens 2006. Paris. 2006. European Nano Systems. 120. 124

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Operation Limits for Mobile Follower. Comunicación en congreso. Nano 2006. Cincinnati. 2006. IEEE Conference on Nanotechnology. 516. 519

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Design Guides for a Correct DC Operation in Rtd-Based Threshold Gates. Comunicación en congreso. IEEE Euromicro Symposium on Digital System Design. Cavtat, Croacia. 2006. Proceedings of IEEE Euromicro Symposium on Digital System Design. 530. 534

Vicerrectorado de Investigación. Universidad de Sevilla. Pabellón de Brasil. Paseo de las Delicias s/n. Sevilla