Logotipo de Universidad de Sevilla
VICERRECTORADO DE INVESTIGACIÓN
Logotipo Andalucía Tech
Letras Universidad de Sevilla

Ficha personal - María José Avedillo de Juan


María José Avedillo de Juan
Telefono: 954466666/954552790
Email: Solicitar correo
Perfil en ORCID: 0000-0002-8345-8441
Perfil en ResearcherID: Q-8001-2018
Perfil en Scopus: 7003834609
Perfil en Dialnet: 2960163

Grupo de Investigación: Diseño y Test de Circuitos Integrados de Señal Mixta
Departamento/Unidad: Electrónica y Electromagnetismo
Situación profesional: Catedrática de Universidad

Responsable de los siguientes proyectos/ayudas en la US:

  • Proyectos:
    • Two-Dimensional Oscillatory Neural Networks for Energy Efficent Neuromorphic computing (NeurONN) (GRANT_AGREEMENT_NO_871501)
    • Circuitos y Arquitecturas con Dispositivos Steep Slope para Aplicaciones de muy Bajo Consumo de Potencia (TEC2017-87052-P)
    • Nano-Arquitecturas para Computación Lógica Usando Dispositivos Emergentes (TEC2013-40670-P)
    • Arquitecturas y Circuitos con Rtds para Aplicaciones Lógicas y no Lineales (TEC2010-18937)

  • Ayudas:
    • Incentivo al Grupo de Investigación TIC-178 (2019/TIC-178)

Participa en los siguientes proyectos/ayudas en la US:

  • Proyectos:
    • Diseño e implementación de circuitos multivaluados usando dispositivos con característica Ndr (P07-TIC-02961 - Investigador)
    • Técnicas de diseño y test de circuitos integrados mixtos en tecnologías emergentes (EXC/2005/TIC-927 - Investigador)

  • Contratos Arts. 68/83 LOU:
    • Microelectrónica: tecnología, diseño y test (OG-123/05 - Investigador)
    • Microelectrónica: tecnología, diseño y test (OG-080/04 - Investigador)
    • Microelectrónica: tecnología, diseño y test (OG-036/03 - Investigador)
    • Microelectrónica: tecnología, diseño y test (OG-020/02 - Investigador)
    • Microelectrónica: tecnología, diseño y test (SPRING-IST-1999-12342) (OG-023/02 - Investigador)
    • Microelectrónica: tecnología, diseño y test (ESPRIT 21458-SIGYRO) (OG-062/00 - Investigador)
    • Microelectrónica: tecnología, diseño y test (ESPRIT 25213-TARDIS) (OG-063/00 - Investigador)
    • Microelectrónica: tecnología, diseño y test (ESPRIT 26354-ASTERIS) (OG-067/00 - Investigador)

  • Ayudas:
    • Incentivo al Grupo de Investigación TIC-178 (2017/TIC-178 - Investigador)
    • Incentivo al Grupo de Investigación TIC-178 (2011/TIC-178 - Investigador)
    • Ayuda a la Consolidación del Grupo de Investigación TIC-178 (2009/TIC-178 - Investigador)
    • Ayuda a la Consolidación del Grupo de Investigación TIC-178 (2008/TIC-178 - Investigador)
    • Ayuda a la Consolidación del Grupo de Investigación TIC-178 (2007/TIC-178 - Investigador)
    • Ayuda a la Consolidación del Grupo de Investigación TIC-178 (2006/TIC-178 - Investigador)

Cobertura de la base de datos de proyectos, véase aqui


Publicaciones:

Capítulos en Libros
Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Analytic Approach to the Operation of Rtd Ternary Inverters Based on Mml. Pag. 97-112. En: Cutting Edge Nanotechnology. Rijeka, Croacia. In-Tech. 2010. ISBN 978-953-7619-93-0

Rodriguez Villegas, Esther, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Rueda, a:
Threshold Logic Based Adders Using Floating-Gate Circuits. Pag. 54-58. En: Advances in Physics, Electronics and Signal Processing Application. 2000

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Delay Circuits. Vol. 5. Pag. 127-139. En: Encyclopedia of Electrical and Electronics Engineering. 1999

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Rueda, a:
Threshold Logic. Vol. 22. Pag. 178-190. En: Encyclopedia of Electrical and Electronics Engineering. 1999

Publicaciones en Revistas
Jiménez, Manuel, Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Hybrid Phase Transition FET Devices for Logic Computation. En: IEEE Journal on Exploratory Solid-State Computatio. 2020. Vol. 6. Núm. 1. Pag. 1-8. 10.1109/Jxcdc.2020.2993313

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Nuñez Martínez, Juan:
Phase Transition Device for Phase Storing. En: IEEE Transactions on Nanotechnology. 2020. Pag. 107-112. 10.1109/Tnano.2020.2965243

Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Phase Transition Device for Phase Storing. 2020. Pag. 107-112. 10.1109/Tnano.2020.2965243

Avedillo de, Maria Jose, Jiménez, Manuel, Nuñez Martínez, Juan:
Phase Transition FETs for Improved Dynamic Logic Gates. En: IEEE Electron Device Letters. 2018. Vol. 39. Núm. 11. Pag. 1776-1779. 10.1109/Led.2018.2871855

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Power and Speed Evaluation of Hyper-FET Circuits. En: IEEE Access. 2018. Vol. 7. Pag. 6724-6732. 10.1109/Access.2018.2889016

Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Impact of the RT¿level architecture on the power performance of tunnel transistor circuits. En: International Journal of Circuit Theory and Applications. 2017. Vol. 46. Núm. 3. Pag. 647-655. https://doi.org/10.1002/cta.2398

Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Insights Into the Operation of Hyper-FET-Based Circuits. En: IEEE Transactions on Electron Devices. 2017. Vol. 64. Núm. 9. Pag. 3912-3918. 10.1109/Ted.2017.2726765

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Reducing the impact of reverse currents in tunnel FET rectifiers for energy harvesting applications. En: IEEE Journal of the Electron Devices Society. 2017. Vol. 5. Núm. 6. Pag. 530-534. 10.1109/Jeds.2017.2737598

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs. En: IEEE Transactions on Nanotechnology. 2016. Vol. 16. Núm. 1. Pag. 83-89. 10.1109/Tnano.2016.2629264

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Comparative Analysis of Projected Tunnel and CMOS Transistors for Distinct Logic Applications Areas. En: IEEE Transactions on Electron Devices. 2016. Vol. 63. Núm. 12. Pag. 5012-5020. 10.1109/Ted.2016.2616891

Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Improving speed of Tunnel FETs logic circuits. En: Electronics Letters. 2015. Vol. 51. Núm. 21. Pag. 1702-1704. 10.1049/el.2015.2416

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monoestable to Bistable Logic Elements. En: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014. Vol. 22. Núm. 10. Pag. 2238-2242. 10.1109/Tvlsi.2013.2283306

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Novel Pipeline Architectures based on Negative Differential Resistance Devices. En: Microelectronics Journal. 2013. Vol. 44. Núm. 9. Pag. 807-813. 10.1016/j.mejo.2013.06.012

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Domino inspired MOBILE networks. En: Electronics Letters. 2012. Vol. 48. Núm. 5. Pag. 292-293

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Two-Phase RTD-CMOS Pipelined Circuits. En: IEEE Transactions on Nanotechnology. 2012. Vol. 11. Núm. 6. Pag. 1063-1069. 10.1109/Tnano.2012.2213839

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Simplified single-phase clock scheme for MOBILE networks. En: Electronics Letters. 2011. Vol. 47. Núm. 11. Pag. 648-650

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
RTD-CMOS Pipelined Networks for Reduced Power Consumption. En: IEEE Transactions on Nanotechnology. 2011. Vol. 10. Núm. 6. Pag. 1217-1220

Pettenghi Roldan, Hector, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Improved Nanopipelined Rtd Adders Using Generalized Threshold Gates. En: IEEE Transactions on Nanotechnology. 2011. Vol. 10. Núm. 1. Pag. 155-162

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Efficient Realisation of MOS-Ndr Threshold Logic Gates. En: Electronics Letters. 2009. Vol. 45. Núm. 23. Pag. 1158-1160

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Pettenghi Roldan, Hector, Nuñez Martínez, Juan:
Operation Limits for Rtd-Based Mobile Circuits. En: IEEE Transactions on Circuits and Systems Part I: Fundamental Theory and Applications. 2009. Vol. 56. Núm. 2. Pag. 350-363

Pettenghi Roldan, Hector, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Using Multi-Threshold Threshold Gates in Rtd-Based Logic Design: a Case Study. En: Microelectronics Journal. 2008. Vol. 39. Núm. 2. Pag. 241-247

Romeira, Bruno, Figueiredo, Jose Maria, Slight, T.j:, Wang, L.M., Wasige, E., et. al.:
Synchronisation and Chaos in a Laser Diode Driven by a Resonant Tunnelling Diode. En: IET Optoelectronics. 2008. Vol. 2. Núm. 6. Pag. 211-215

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Pettenghi Roldan, Hector:
Self-Latching Operation of Mobile Circuits Using Series-Connection of Rtds and Transistors. En: IEEE Transactions on Circuits and Systems Part II: Analog and Digital Signal Processing. 2006. Vol. 53. Núm. 5. Pag. 334-338

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Pettenghi Roldan, Hector:
Increased Logic Functionality of Clocked Series-Connected Rtds. En: IEEE Transactions on Nanotechnology. 2006. Vol. 5. Núm. 5. Pag. 606-611

Pettenghi Roldan, Hector, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Single Phase Clock Scheme for Mobile Logic Gates. En: Electronics Letters. 2006. Vol. 42. Núm. 24. Pag. 1382-1383

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Transistor Critical Sizing in Mobile Follower. En: Electronics Letters. 2005. Vol. 41. Núm. 10. Pag. 583-584

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Analysis of Frequency Divider Rtd Circuits. En: IEEE Transactions on Circuits and Systems Part I: Fundamental Theory and Applications. 2005. Vol. 52. Núm. 10. Pag. 2234-2247

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, El Alami, H:
Weighted Order Statistics Filter for Real-Time Signal Processing Applications Based on Pass Transistor Logic. En: IEE Proceedings. Circuits, Devices and Systems. 2004. Vol. 151. Núm. 1. Pag. 31-36

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Nonlinear Dynamics in Frequency Divider Rtd Circuits. En: Electronics Letters. 2004. Vol. 40. Núm. 10. Pag. 586-587

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Huertas Diaz, Jose Luis:
Simplified Reed-Muller Expressions for Residue Threshold Functions. En: Circuits, Systems and Signal Processing. 2004. Vol. 23. Núm. 1. Pag. 45-56

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, El Alami, H, Jiménez Calderón, A.:
A Practical Parallel Architecture for Stacks Filters. En: Journal of VLSI Signal Processing. 2004. Vol. 38. Núm. 2. Pag. 91-100

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Jiménez Naharro, Raúl:
Pass-Transistor Based Implementations of Threshold Logic Gates for WOS Filtering. En: Microelectronics Journal. 2004. Vol. 35. Núm. 11. Pag. 869-873

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Pettenghi Roldan, Hector, Kelly, R, Thompson, C.J.:
Multi-Threshold Threshold Logic Circuit Design Using Resonant Tunnelling Devices. En: Electronics Letters. 2003. Vol. 39. Núm. 21. Pag. 1502-1504

Beiu, V, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Review/Reseña: VLSI Implementations of Threshold Logic - a Comprehensive Survey. En: IEEE Transactions on Neural Networks. 2003. Vol. 14. Núm. 5. Pag. 1217-1243

Martínez, N, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Huertas Diaz, Jose Luis:
Copas: a New Algorithm for the Partial Input Encoding Problem. En: VLSI Design. 2002. Vol. 14. Núm. 2. Pag. 171-181

Rodriguez Villegas, Esther, Huertas Sánchez, Gloria, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Rueda, a:
A Practical Floating-Gate Muller-C Element Using Vmos Threshold Gates. En: IEEE Transactions on Circuits and Systems Part II: Analog and Digital Signal Processing. 2001. Vol. 48. Núm. 1. Pag. 102-106

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Huertas Diaz, Jose Luis:
Efficient Realization of a Threshold Voter for Self-Purging Redundancy. En: Journal of Electronic Testing. 2001. Vol. 17. Núm. 1. Pag. 69-73

Rodriguez Villegas, Esther, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Huertas Sánchez, Gloria, Rueda, a:
Nu MOS-Based Sorter for Arithmetic Applications. En: VLSI Design. 2000. Vol. 11. Núm. 2. Pag. 129-136

Rodriguez Villegas, Esther, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Rueda, a:
Sorting Networks Implemented As Vmos Circuits. En: Electronics Letters. 1998. Vol. 34. Núm. 23. Pag. 2237-2238

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Rueda, a:
Low-Cost Bsa Technique for Threshold-Logic Gate Based Multiplier Implementations. En: Electronics Letters. 1997. Vol. 33. Núm. 12. Pag. 1028-1030

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Huertas Diaz, Jose Luis:
Efficient State Reduction Methods for PLA-based Sequential Circuits. En: IEEE Proceedings. Computers and Digital Techniques. 1992. Vol. 139. Pag. 491-500

Huertas Diaz, Jose Luis, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Area Optimised Registers by Using a Folded PLA. En: IEE Proceedings. Circuits, Devices and Systems. 1990. Vol. 137. Pag. 28-32

Aportaciones a Congresos
Jiménez, Manuel, Nuñez Martínez, Juan, Avedillo de, Maria Jose:
An Approach to the Device-Circuit Co-Design of HyperFET Circuits. Comunicación en congreso. International Symposium on Circuits and Systems. Sevilla, España. 2020

Nuñez Martínez, Juan, Jiménez, Manuel, Avedillo de, Maria Jose:
Device circuit co-design of HyperFET transistors. Comunicación en congreso. 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS). Bilbao (España). 2019

Quintero Alvarez, Héctor Javier, Jiménez, Manuel, Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Inverting versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. Comunicación en congreso. 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. - Praga, República Checa. 2018

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Exploring Logic Architectures Suitable for TFETs Devices. Comunicación en congreso. 2017 IEEE International Symposium on Circuits and Systems (ISCAS). Baltimore, MD, USA. 2017

Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Impact of Pipeline in the Power Performance of Tunnel Transistor Circuits. Comunicación en congreso. 26th International Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS). Bremen, Alemania. 2016

Calahorro, Jose Manuel, Acasandrei, Laurentiu, Barriga Barros, Angel, Avedillo de, Maria Jose:
Experiencia en desarrollo de sistemas empotrados hardware-software como Trabajo Fin de Grado. Comunicación en congreso. XII Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica. Sevilla (España). 2016

Nuñez Martínez, Juan, Avedillo de, Maria Jose:
Complementary Tunnel Gate Topology to Reduce Crosstalk Effects. Comunicación en congreso. XXXI Conference on Design of Circuits and Integrated Systems DCIS 2016. Granada. 2016

Avedillo de, Maria Jose, Barriga Barros, Angel, Acasandrei, Laurentiu, Calahorro, Jose Manuel:
Hardware-Software Embedded Face Recognition System. Poster en Congreso. 24th International Conference in Central Europe on Computer Graphics, Visualization and Computer Vision. Plzen, Czech Republic. 2016

Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Assessing application areas for tunnel transistor technologies. Comunicación en congreso. Design of Integrated Circuits and Systems 2015. Lisboa. 2015

Quintero Alvarez, Héctor Javier, Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Improving robustness of dynamic logic based pipelines. Comunicación en congreso. Design of Circuits and Integrated Systems 2015. 2015

Nuñez Martínez, Juan, Quintero Alvarez, Héctor Javier, Avedillo de, Maria Jose:
DOE based high-performance gate-level pipelines. Comunicación en congreso. Powe and Timming Modeling, Optimization and Simulation International Workshop. Palma de Mallorca. 2014

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Quintero Alvarez, Héctor Javier:
Improving delay-noise trade-off of dynamic gates for fine-grained pipelined applications. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems. 2013

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Novel dynamic gate topology for superpipelines in DSM technologies. Comunicación en congreso. Digital System Design EUROMICRO. Santander. 2013

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits. Comunicación en congreso. IBERCHIP 2012. Playa del Carmen, Mexico. 2012

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Compact and Power Efficient MOS-NDR Muller C-Elements. Comunicación en congreso. Doctoral Conference on Computing, Electrical and Industrial Systems. Caparica (Lisboa). 2012

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications. Comunicación en congreso. International Workshop on Power and Timing Modeling, Optimization and Simulation. NEWCASTLE, REINO UNIDO, United Kingdom. 2012

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits. Comunicación en congreso. IEEE International Conference on Electronics, Circuits, and Systems. Sevilla, España. 2012

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs. Comunicación en congreso. SPIE 2011. Praga, República Checa. 2011

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Efficient Realization of RTD-CMOS Logic Gates. Comunicación en congreso. Great Lakes Symposium on VLSI. Laussane, Suiza. 2011

Pettenghi Roldan, Hector, Chaves, Ricardo, Sousa, Lionel, Avedillo de, Maria Jose:
An Improved Rns Generator 2n ± K Based on Threshold Logic. Comunicación en congreso. IEEE/Ifip VLSI-SOC. 2010

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Evaluation of Rtd-CMOS Logic Gates. Comunicación en congreso. DSD Euromicro 2010. Lille, Francia. 2010. DSD Euromicro 2010. 621. 627

Nuñez Martínez, Juan, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Single Phase MOS-Ndr Mobile Networks. Comunicación en congreso. IEEE International Symposium on Circuits and Systems, ISCAS, pp. 1979-1982, Jun. 201. Paris, France. 2010. Proceedings of 2010 IEEE International Symposium on Circuits Ans Systems (ISCAS). 153. 156

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Redes Mobile MOS-Ndr Operando con Reloj de una Fase. Comunicación en congreso. IBERCHIP 2010. Iguazú (Brasil). 2010. IBERCHIP 2010. 145. 148

Pettenghi Roldan, Hector, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Single Phase Clock Scheme for Mobile Based Circuits. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems. Zaragoza. 2009. XXI Conference on Design of Circuits and Integrated Systems. --. --

Bol, D, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Legat, J.D.:
Mobile Digital Circuits Based on Negative-Differential-Resistance MOS Structures. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems. Zaragoza. 2009. XXI Conference on Design of Circuits and Integrated Systems. 39. 42

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
DC Operation Limits for Mobile Inverters. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems. Zaragoza. 2009. XXI Conference on Design of Circuits and Integrated Systems. --. --

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Muller C-Elements Multientrada Basados en MOS-Ndr. Comunicación en congreso. IBERCHIP. Buenos Aires, Argentina. 2009. IBERCHIP 2009. -. -

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Pettenghi Roldan, Hector, Nuñez Martínez, Juan:
Puertas Umbral Generalizadas para el Diseño Lógicos de Circuitos Mobile. Comunicación en congreso. IBERCHIP. Buenos Aires, Argentina. 2009. IBERCHIP 2009. -. -

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Fast and Area Efficient Multi-Input Muller C-Element Based on MOS-Ndr. Comunicación en congreso. IEEE International Symposium on Circuits and Systems. Taipei, Taiwan. 2009. IEEE International Symposium on Circuits and Systems. 1811. 1814

Pettenghi Roldan, Hector, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
A Novel Contribution to the Rtd-Based Threshold Logic Family. Poster en Congreso. ISCAS 2008. Seattle, Washington, USA. 2008. IEEE International Symposium on Circuits and Systems. 2350. 2353

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Analysis of the Critical Rise Time in Mobile-Based Circuits. Poster en Congreso. IEEE Icecs. Malta. 2008. IEEE International Conferenec on Electronics Circuit and Systems. 938. 941

Pettenghi Roldan, Hector, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Rtd Based Logic Circuits Using Generalized Threshold. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems. Grenoble (Francia). 2008

Romeira, Bruno, Figueiredo, Jose Maria, Slight, T.j:, Wang, L.M., Wasige, E., et. al.:
Observation of Frequency Division and Chaos Behavior in a Laser Diode Driven by a Resonant Tunneling Diode. Comunicación en congreso. Cleo/Qels 2008. Dd. 2008. Conference on Lasers and Electro-Optics, 2008 and 2008 Conference on Quantum Electronics and Laser Science. 1. 2

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Limits to a Correct Operation in Rtd-Based Ternary Inverters. Comunicación en congreso. ISCAS 2008. Seattle, Washington, USA. 2008. IEEE International Symposium on Circuits and Systems. 604. 607

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Design of Rtd-Based Nmin/Nmax Gates. Comunicación en congreso. IEEE Nano 2008. Arlingtong, Tx, USA. 2008. 8th IEEE Conference on Nanotechnology, 2008. . 518. 521

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Transient Response in Mobile-Based Circuits. Comunicación en congreso. VLSI-SOC. Rhodes Island, Greece. 2008. International Conference on Very Large Scale Integration. S. N

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
A Quasi Differential Quantizer Based on Smobile. Comunicación en congreso. IEEE Symposium on Integrated Circuits and Systems Design . Río de Janeiro (Brazil). 2008. IEEE Proceedings of the 20th Symposium on Integrated Circuits and Systems Design (Sbcci'2007). 251. 256

Pettenghi Roldan, Hector, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Non Return Mobile Logic Family. Comunicación en congreso. IEEE International Symposium on Circuits and System. New Orleans, Lusiana, USA. 2007

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Correct Operation in Smobile-Based Quasi-Differential Quantiziers. Comunicación en congreso. ECCTD 2007. Santander (ESPAÑA). 2007. ECCTD 2007: European Conference on Cicuit Theory and Design. 930. 933

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
DC Operation Limits of Rtd Ternary Inverters Based on Nml. Comunicación en congreso. DCIS. Santander (ESPAÑA). 2007. DCIS 2007. 311. 316

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Analytic Approach to the Operation of Rtd Ternary Inverters Based on Mml. Comunicación en congreso. International Workshop on Post-Binary Ulsi Systems. Oslo (Norway). 2007. International Workshop on Post-Binary Ulsi Systems. --. --

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Operation Limits in Rtd-Based Ternary Quantizers. Comunicación en congreso. ACM Great Lakes Symposium on VLSI. Stressa-Lago Maggiore (Italy). 2007. ACM Great Lakes Symposium on VLSI (Glsvlsi'2007). 114. 119

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Limits to a Correct Evaluation in Rtd-Based Quaternary Inverters. Comunicación en congreso. International Symposium on Multiple-Valued Logic. Oslo (Norway). 2007. International Symposium on Multiple-Valued Logic (Ismvl'2007). 51. 56

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Correct DC Operation in Rtd Based Ternary Inverters. Comunicación en congreso. IEEE International Conference of Nano/Micro Engineered and Molecular Systems. Bangkok (Thailandia). 2007. IEEE International Conference of Nano/Micro Engineered and Molecular Systems (Nems'2007). 860. 865

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Holding Preserving in Rtd-Based Multiple-Valued Quantiziers. Comunicación en congreso. IEEE Conference on Nanotechnology . Hong-Kong (China). 2007. IEEE Conference on Nanotechnology (IEEE Nano'2007). --. --

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Nuñez Martínez, Juan:
Design Guides for a Correct DC Operation in Rtd-Based Threshold Gates. Comunicación en congreso. IEEE Euromicro Symposium on Digital System Design. Cavtat, Croacia. 2006. Proceedings of IEEE Euromicro Symposium on Digital System Design. 530. 534

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Pettenghi Roldan, Hector:
Implementación de Lógica Umbral y Multiumbral con Rtds. Comunicación en congreso. IBERCHIP. San Jose, Costa Rica. 2006. XII Workshop IBERCHIP. --. --

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Pettenghi Roldan, Hector:
Self-Latching Operation Limits for Mobile Circuits. Comunicación en congreso. ISCAS 2006. Kos, Grecia. 2006. IEEE International Symposium on Circuiits and Systems. 4579. 4582

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Holding Dissapearance in Rtd-Based Quantizers. Comunicación en congreso. Ens 2006. Paris. 2006. European Nano Systems. 120. 124

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Limits to a Correct Evaluation in Rtd Based Ternary Inverters. Comunicación en congreso. Icecs. Nice (France). 2006. IEEE International Conference on Electronics , Circuits, and Systems. 403. 406

Bol, D, Legat, J.D., Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Monostable-Bistable Transition Logic Elements: Threshold Logic Vs. Boolean Logic Comparison. Comunicación en congreso. Icecs. Nice (France). 2006. IEEE International Conference on Electronics , Circuits, and Systems. 1049. 1052

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Nuñez Martínez, Juan:
DC Correct Operation in Mobile Inverters. Comunicación en congreso. Mwcas 2006. San Juan (Puerto Rico). 2006. 49th Midwest Symposium on Circuits and Systems. --. --

Nuñez Martínez, Juan, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Operation Limits for Mobile Follower. Comunicación en congreso. Nano 2006. Cincinnati. 2006. IEEE Conference on Nanotechnology. 516. 519

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Operation Limits for Mobile Followers. Comunicación en congreso. Nano 2006. Cincinnati. 2006. IEEE Conference on Nanotechnology. 516. 519

Pettenghi Roldan, Hector, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Nanopipelined Rtd Adders Using Multi-Threshold Threshold Gates. Comunicación en congreso. Conference on Design of Circuits and Integrated Systems DCIS 2005 . Lisboa. 2005

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Huertas Diaz, Jose Luis:
Robust Frequency Divider Based on Resonant Tunneling Devices. Comunicación en congreso. IEEE International Symposium on Circuits and Systems: ISCAS 2005. Kobe, Japón. 2005. ISCAS 2005. IEEE International Symposium on Circuits and Systems: Conference Proceedings. 2647. 2650

Pettenghi Roldan, Hector, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Using Multi-Threshold Gates in Rtd-Based Logic Design. Comunicación en congreso. European Nano Systmes Conference. París, Francia. 2005. Proceedings of the European Nano Systems Conference (Ens 2005). --. --

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Pettenghi Roldan, Hector:
Logic Models Supporting the Design of Mobile-Based Rtd Circuits. Comunicación en congreso. IEEE International Conference on Application-Specific Systems, Architecture Processors. Samos, Grecia. 2005. Asap 2005: 16th International Conference on Application-Specific Systems, Architecture and Processors, Proceedings. 254. 259

Pettenghi Roldan, Hector, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
New Circuit Topology for Logic Gates Based on Rtd's. Comunicación en congreso. IEEE Conference on Nanotechnology. Nagoya, Japón. 2005. Proceedings of the 5th IEEE Conference on Nanotechnology. 283. 286

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Pettenghi Roldan, Hector:
Rtd-Based Compact Programmable Gates. Comunicación en congreso. International Joint Conference on Neural Networks. Budapest, Hungría. 2004. Proceedings of the International Joint Conference on Neural Networks (Ijcnn 2004). 2637. 2640

Pettenghi Roldan, Hector, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
A CAD Tool for the Design of Rtd Programmable Gates Based on Mobile. Comunicación en congreso. Design of Circuits and Integrated Systems Conference. Bordeaux, Francia. 2004. Proceedings of the XIX Conference on Design of Circuits and Integrated Systems, DCIS 2004. 25. 30

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
A Threshold Logic Synthesis Tool for Rtd Circuits. Comunicación en congreso. Euromicro Systems on Digital System Design. Rennes, Francia. 2004. Proceedings of the Euromicro Systems on Digital System Design (Dsd'04). 624. 627

Pettenghi Roldan, Hector, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Useful Logic Blocks on Clocked Series-Connected Rtds. Comunicación en congreso. 4th IEEE Conference on Nanotechnology. Munich, Alemania. 2004. Proceedings of 4th IEEE Conference on Nanotechnology (Ieee_nano 2004). -. -

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Pettenghi Roldan, Hector:
Programmable Logic Gate Based on Resonant Tunneling Devices. Comunicación en congreso. 2004 IEEE International Symposium on Circuits and Systems. Vancouver, Canada. 2004

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Pettenghi Roldan, Hector, El Alami, H:
Design of Residue Generators Modulo-3 Using Threshold Logic. Comunicación en congreso. Conferencia de Diseño de Circuitos Integrados y Sistemas. Ciudad Real. 2003. Proceedings of the XVIII International Conference on Design of Circuits and Integrated Systems. 166. 171

Beiu, V, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Andonie, R:
Differential Implementations of Threshold Logic Gates. Comunicación en congreso. International Symposium on Signals, Circuits and Systems. Iasi, Rumanía. 2003. Proceedings of the International Symposium on Signals, Circuits and Systems (SCS 2003). 489. 492

Beiu, V, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Review of Capacitive Threshold Gate Implementations. Comunicación en congreso. International Conference on Artificial Neural Networks. Estambul, Turquía. 2003. Proceedings of International Conference on Artificial Neural Networks (ICANN 2003). 737. 744

Beiu, V, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Review of Differential Threshold Gate Implementations. Comunicación en congreso. Iasted International Conference on Neural Networks and Computational Intelliegence. Tijuana, Méjico. 2003. Proceedings of Iasted International Conference on Neural Networks and Computational Intelliegence (Nci 2003). 0. 0

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Beyond Threshold Logic: Multi-Threshold Threshold Logic. Comunicación en congreso. Mel-Ari-Nid Workshop. Toulouse, Francia. 2003. Proceedings of Mel-Ari-Nid Workshop 2003. 0. 0

Vazquez Garcia de la Vega, Diego, Huertas Sánchez, Gloria, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Rueda Rueda, Adoracion, et. al.:
A Lp-LV High Performance Monolitic DTMF Receiver With on-Chip Test Facilities. Comunicación en congreso. Spie's International Symposium on Microtechnologies for the New Millenium. Mas Palomas, Gran Canaria, España. 2003

Linares Barranco, Bernabe, Rodriguez Villegas, Esther, Martínez Pérez, Manuel, Leger, Gildas, Guerra Gutiérrez, Pedro, et. al.:
A VHDL Behavioural Model for Pipeline Adcs. Comunicación en congreso. Nuevas Perspectivas en la Intervencion Psicopedagogica: II. Orientacion, Educaion Especial y Formacion del Profesorado. 2002. XXV Reunión de la Asociación Española de Ciencia Regional. 0. 0

Martínez Pérez, Manuel, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Koegst, M, Ruelke, S, et. al.:
An Encoding Technique for Low Power CMOS Implementations of Controllers. Comunicación en congreso. Design, Automation Test in Europe. Paris. 2002. Date Conference 2002. 1083. 1083

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Rodriguez Villegas, Esther, Rueda, a:
Threshold-Logic-Based Design of Compressors. Comunicación en congreso. International Conference on Electronic Circuits and Systems. Dubrovnik, Croacia. 2002. Icecs Conference 2002. 661. 664

Avedillo de, Maria Jose, Rueda, a:
Simple Parallel Weighted Order Statistic Filter Implementations. Conferencia Congreso no publicada. IEEE International Symposium on Circuits and Systems. -. 2002. 2002 IEEE International Symposium on Circuits and Systems. 607. 610

Rodriguez Villegas, Esther, Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Rueda, a:
High-Speed Low-Power Logic Gates Using Floating Gates. Conferencia Congreso no publicada. IEEE International Symposium on Circuits and Systems. -. 2002. 2002 IEEE International Symposium on Circuits and Systems. 389. 392

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Huertas Diaz, Jose Luis:
Simplified Reed-Muller Expressions for Residue Threshold Functions. Conferencia Congreso no publicada. IEEE International Symposium on Circuits and Systems. -. 2002. 2002 IEEE International Symposium on Circuits and Systems. 599. 602

Vazquez Garcia de la Vega, Diego, Avedillo de, Maria Jose, Huertas Sánchez, Gloria, Quintana Toledo, Jose Maria, Pauristsch, M, et. al.:
A Low-Voltage Low-Power High Performance Fully Integrated DTMF Receiver. Comunicación en congreso. European Solid-State Circuits Conference. Villach, Austria. 2001. Esscirc'2001. 368. 371

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose:
Reed-Muller Description of Symmetric Functions. Comunicación en congreso. IEEE International Symposium on Circuits and Systems. Sydney. 2001. ISCAS Symposium 2001. 682. 685

Martínez Pérez, Manuel, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Huertas Diaz, Jose Luis:
A Flexible State Assignment Algorithm for Low Power Implementations. Comunicación en congreso. Proc. Design Circuits and Integrated Systems Conference. Oporto. 2001. DCIS Conference 2001. 154. 159

Koegst, M, Ruelke, S, Susse, H, Franke, G, Avedillo de, Maria Jose:
Two-Criterial Constrain-Driven FSM State Encoding for Low Power. Comunicación en congreso. Euromicro Symposium on Digital Systems. 2001. Euromicro Symposium 2001. 94. 99

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Rodriguez Villegas, Esther:
Improved Compressor Designs Bases on Threshold Logic. Comunicación en congreso. Seminario Anual de Automática, Electrónica Industrial e Instrumentación. Saaei 2001. Matanzas, Cuba. 2001. Saaei Seminario 2001. 0. 0

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Jiménez Naharro, Raúl, Rodriguez Villegas, Esther:
Practical Low-Cost CPL Implemenations of Threshold Logic Functions. Comunicación en congreso. Glsvlsi. 2001. Glsvlsi Conference 2001. 139. 144

Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Jiménez Naharro, Raúl:
Pass Transistor Threshold Gates. Applications to WOS Filters. Comunicación en congreso. International Workshop on Logic & Synthesis. Granlibakken, California. 2001. Iwls Workshop 2001. 78. 83

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Jiménez Naharro, Raúl, Rodriguez Villegas, Esther:
Low-Power Logic Styles for Full-Adder Circuits. Comunicación en congreso. International Conference on Electronics, Circuits and Systems. Malta. 2001. Icecs Conference 2001. 1417. 1420

Martínez Pérez, Manuel, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Huertas Diaz, Jose Luis:
New Ideas on Face Constrained Generation. Comunicación en congreso. Design of Integrated Circuits and Systems DCIS 2000. Montpellier, Francia. 2000. Dcis'2000. 519. 524

Martínez Pérez, Manuel, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Koegst, M, Ruelke, S, et. al.:
New Low Power State Assignment Approach. Comunicación en congreso. Design of Integrated Circuits and Systems DCIS 2000. Montpellier, Francia. 2000. Dcis'2000. 181. 187

Rueda Rueda, Adoracion, Avedillo de, Maria Jose, Guerra, P., Quintana Toledo, Jose Maria, Serra, F., et. al.:
Diseño e Implementacion de un Biofono Digital CMOS de Bajo Consumo. Comunicación en congreso. Seminario del Programa Nacional de Tecnologias de la Informacion y las Comunicaciones (Tedea2000). 2000. Actas del seminario TEDEA'2000. 55. 58

Koegst, M, Ruelke, S, Martínez Pérez, Manuel, Susse, H, Avedillo de, Maria Jose, et. al.:
Combination of Two Approaches for Low Power Design of Controllers. Comunicación en congreso. International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia, Polonia. 2000. Mixdes'2000. 227. 232

Rodriguez Villegas, Esther, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Rueda Rueda, Adoracion:
Efficient Vmos Realization of Treshold Voters for Self-Purging Redundancy. Comunicación en congreso. Brazilian Symposium on Integrated Circuit Design. Brasil. 2000. Brazilian Symposium on Integrated Circuit Design. 321. 326

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Rodriguez Villegas, Esther, Rueda Rueda, Adoracion:
Vmos-Based Compressor Designs. Comunicación en congreso. International Conference on Microelectronics. Teherán. 2000. Icm'2000. 33. 36

Rodriguez Villegas, Esther, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Huertas Sánchez, Gloria, Rueda Rueda, Adoracion:
Vmos-Based Sorters for Multiplier Implementation. Comunicación en congreso. International Symposium on Circuits and Sysetms. Orlando, Florida. 1999. ISCAS Symposium 1999. 338. 341

Martínez Pérez, Manuel, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Huertas Diaz, Jose Luis:
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. Comunicación en congreso. Design, Automation and Test in Europe. Munich. 1999. Date Conference 1999. 521. 526

Martínez Pérez, Manuel, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Huertas Diaz, Jose Luis:
A Dynamic Model for the State Assignment. Comunicación en congreso. Design Automation and Test in Europe. Paris. 1998. Date Conference 1998. 835. 839

Martínez Pérez, Manuel, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria, Huertas Diaz, Jose Luis:
Picola: a Novel Column-Based Algorithm for Partial Encoding Problems. Comunicación en congreso. Design of Circuits and Integrated Systems Conference, DCIS 98. 1998. Proceedings DCIS CONFERENCE 1998. 278. 283

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Parra Fernández, María del Pilar, Huertas Diaz, Jose Luis:
Optimum Pla Folding Through Boolean Satisfiability. Comunicación en congreso. Asia and South Pacific Design Automation Conference. Japon. 1995. Proceedings of Asia and South Pacific Design Automation Conference. 289. 293

Quintana Toledo, Jose Maria, Avedillo de, Maria Jose, Rueda Rueda, Adoracion, Baena Oliva, Maria Carmen, Huertas Diaz, Jose Luis:
Practical Low-Cost CMOS Realization of Complex Logic Functions. Comunicación en congreso. European Conference on Circuit Theory and Design. Estambul, Turquía. 1995. Proc. European Conference on Circuit Theory and Design. 51. 54

Parra Fernández, María del Pilar, Avedillo de, Maria Jose, Quintana Toledo, Jose Maria:
Plegado Óptimo de Plas Mediante Satisfactoriedad Booleana. Comunicación en congreso. IX Congreso de Diseño de Circuitos Integrados. Gran Canaria. 1994. DCIS 94. 523. 528

Quintana Toledo, Jose Maria, Rueda Rueda, Adoracion, Avedillo de, Maria Jose, Baena Oliva, Maria Carmen:
Diseño Eficiente de un Elemento-C de Muller Basado en Puertas Umbral. Comunicación en congreso. IX Congreso de Diseño de Circuitos Integrados. Gran Canaria. 1994. DCIS 94. 477. 481

Tesis dirigidas y co-dirigidas:


(Doctorando no grabado)
Desarrollo y Evaluación de Arquitecturas Lógicas Basadas en Nanopipeline. Tesis Doctoral. 2018

Nuñez Martínez, Juan:
Diseño lógico de circuitos digitales usando dispositivos con característica NDR. Tesis Doctoral. 2011

Pettenghi Roldan, Hector:
Una Aportacion al Diseño Digital Usando Dispositivos Basados en Efecto Tuney Resonante. Tesis Doctoral. 2009

Martínez Pérez, Manuel:
Algoritmos de Codificación Binaria de Símbolos para la Síntesis Lógica de Circuitos Integrados Digitales. Tesis Doctoral. 2003

Vicerrectorado de Investigación. Universidad de Sevilla. Pabellón de Brasil. Paseo de las Delicias s/n. Sevilla